Secure access to peripheral devices over a bus
US10095891B2 · kind B2 · utility
5Cited by
5References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2016 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | Nov 30, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4282
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes an interface and a processor. The interface is configured for communicating over a bus. The processor is configured to disrupt on the bus a transaction in which a bus-master device attempts to access a peripheral device without authorization, by forcing one or more dummy values on at least one line of the bus in parallel to at least a part of the transaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.