Multi GPU interconnect techniques
US10096078B2 · kind B2 · utility
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14Claims
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Key dates
| Filing date | Aug 13, 2013 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | Aug 13, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A graphics processing subsystem includes one or more memory devices and two or more graphics processing units (GPU). The graphics processing units each include a memory interface. A first sub-set of the memory interface of the first graphics processing unit communicatively couples the first graphics processing unit to the first memory device. A first sub-set of the memory interface of the second graphics processing unit is connected to a second sub-set of the memory interface of the first graphics processing unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.