Data compaction and memory bandwidth reduction for sparse neural networks
US10096134B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2017 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | Jun 2, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/082
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, computer program product, and system for sparse convolutional neural networks that improves efficiency is described. Multi-bit data for input to a processing element is received at a compaction engine. The multi-bit data is determined to equal zero and a single bit signal is transmitted from the memory interface to the processing element in lieu of the multi-bit data, where the single bit signal indicates that the multi-bit data equals zero. A compacted data sequence for input to a processing element is received by a memory interface. The compacted data sequence is transmitted from the memory interface to an expansion engine. Non-zero values are extracted from the compacted data sequence and zeros are inserted between the non-zero values by the expansion engine to generate an expanded data sequence that is output to the processing element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.