Display system
US10096302B2 · kind B2 · utility
3Cited by
6References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2015 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | Jun 14, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2340/0435
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display system is provided. The display system includes a perframe controller configured to receive a frame synchronization signal and to change values of M and N in synchronization with at least one pulse of the frame synchronization signal, where M and N are natural numbers; and a fractional divider configured to generate and output a pixel clock signal by dividing an input clock signal by a division ratio of N/M.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.