Host and multi-display system including the same
US10096303B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2015 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | Nov 19, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2370/042
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system on chip (SoC) for transmitting data packets to a display driver integrated circuit (IC) controlling a plurality of displays is provided. The SoC includes a first register, and a central processing unit (CPU) configured to set first values in the first register to adjust a frame rate of each of the displays. A tearing effect (TE) signal detection circuit is configured to detect a TE signal output from the display driver IC. A data transmission circuit is configured to generate a plurality of frame rate adjustment signals using the detected TE signal and the first values and to control transmission timings of the data packets transmitted to the displays using the frame rate adjustment signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.