Multiple barrier layer encapsulation stack
US10096533B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2015 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | Nov 17, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2201/501
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for encapsulating an apparatus to restrict environmental element permeation between the apparatus and an external environment includes applying multiple barrier layers to the apparatus and preceding each layer application with a separate cleaning of the presently-exposed apparatus surface, resulting in an apparatus which includes an encapsulation stack, where the encapsulation stack includes a multi-layer stack of barrier layers. Each separate cleaning removes particles from the presently-exposed apparatus surface, exposing gaps in the barrier layer formed by the particles, and the subsequently-applied barrier layer at least partially fills the gaps, so that a permeation pathway through the encapsulation stack via gap spaces is restricted. The quantity of barrier layers applied to form the stack can be based on a determined probability that a stack of the particular quantity of barrier layers is independent of at least a certain quantity of continuous permeation pathways through the stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.