Fan-out semiconductor package
US10096552B2 · kind B2 · utility
1Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2017 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | Aug 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fan-out semiconductor package includes: a first semiconductor chip; a first encapsulant; a connection member including first vias and a first redistribution layer; a second semiconductor chip; a second encapsulant; a second redistribution layer; second vias; and third vias. A length of the longest side of a first cut surface of the second via is less than that of the longest side of a second cut surface of the third via, the first cut surface of the second via and the second cut surface of the third via being cut by a plane on any level parallel to the second active surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.