Three dimensional memory device having isolated periphery contacts through an active layer exhume process
US10096612B2 · kind B2 · utility
3Cited by
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20Claims
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Key dates
| Filing date | Sep 14, 2015 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | Sep 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three dimensional memory device is described having an array region and a periphery region. The array region has a three dimensional stack of storage cells. The periphery region has contacts that extend from above the three dimensional stack of storage cells to below the three dimensional stack of storage cells. The periphery region is substantially devoid of conducting and/or semi-conducting layers of the three dimensional stack of storage cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.