Pixel array substrate
US10096627B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2017 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | Dec 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H29/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A pixel array substrate includes a display area, signal lines, transmission lines, selection lines, and jumper wires. The selection lines intersect with the signal lines to form intersection regions. The selection lines have first contacts, second contacts, and third contacts. The first contacts are respectively located on the intersection regions. Each of the first contacts is between one of the second contacts and one of the third contacts. A first portion of the first contacts are passed by a line of the display area. The jumper wires respectively pass the first contacts, and two ends of each of the jumper wires are respectively located on one of the second contacts and one of the third contacts. A first portion of the jumper wires electrically connect the first portion of the first contacts and the second contacts, but electrically isolate the third contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.