Semiconductor element and fabrication method thereof
US10096746B2 · kind B2 · utility
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Key dates
| Filing date | May 27, 2017 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | May 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/841
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor element includes a super-lattice buffer layer including AlxN1-x layers and AlyO1-y layers (0<x<1, 0<y<1). The super-lattice buffer layer can mitigate corrosion to the side wall by chemical solution during chip fabrication, and improve chip yield. Fabrication the super-lattice buffer layer to achieve the effects can be realized, for example, using chemical vapor deposition (CVD).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.