Methods for fabricating a memory device with an enlarged space between neighboring bottom electrodes
US10096772B2 · kind B2 · utility
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8Claims
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Key dates
| Filing date | Nov 5, 2015 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | Nov 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/823
Abstract
Embodiments of the present invention describe a method for fabricating a memory device comprising an enlarged space between neighboring bottom electrodes comprising depositing a poly-silicon layer on a substrate depositing a carbon layer above the poly-silicon layer, patterning a photo-resist layer on the carbon layer, depositing a first spacer layer on the photo-resist layer and performing a modified photolithography process on the photo resist layer after etching back the spacer layer creating sidewalls.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.