Reducing undesirable capacitive coupling in transistor devices

US10096788B2 · kind B2 · utility

Assignee

• Flexenable Limited · GB

Inventor

• Jan Jongman · Cambridge, GB

Key dates

• Filing date: Dec 9, 2014
• Grant date: Oct 9, 2018
• Expiry date: Dec 9, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10K71/621

Abstract

A transistor device comprising: source and drain conductors connected by a semiconductor channel; and a gate conductor capacitively coupled to the semiconductor channel via a gate dielectric; wherein the gate conductor comprises at least one portion overlapping at least part of at least one of said source and drain conductors; and further comprising a patterned insulator interposed between at least part of said at least one of the source and drain conductors and said at least one overlapping portion of said gate conductor so as to reduce capacitive coupling between the said at least one of the source and drain conductors and the gate conductor by more than any reduction in capacitive coupling between the semiconductor channel and the gate conductor.