Three-level voltage bus apparatus and method
US10097109B1 · kind B1 · utility
3Cited by
2References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 19, 2017 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | Jul 19, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M7/4833
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a first switch and a first capacitor connected in series between a first voltage bus and a second voltage bus, a second capacitor and a second switch connected in series between the first voltage bus and the second voltage bus and a diode coupled between a common node of the first switch and the first capacitor, and a common node of the second capacitor and the second switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.