Monolithic attenuator, limiter, and linearizer circuits using non-linear resistors
US10097164B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2016 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | Dec 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/451
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Monolithic attenuator, limiter, and linearizer circuitry to be integrated with other circuitry on a chip are provided. According to one aspect, a monolithic attenuator and limiter circuit comprises an input terminal, an output terminal, a first resistor having a first terminal coupled to the input terminal and a second terminal coupled to the output terminal, and a second resistor having a first terminal coupled to the first or second terminal of the first resistor and a second terminal coupled to ground. At least the first resistor is a non-linear resistor whose resistance changes as a function of the voltage across the resistor. The monolithic attenuator and limiter circuit may be part of a “Pi” or “Tee” topology. According to another aspect, a non-linear shunt resistor coupled to the input of an amplifier circuit can operate to linearize the gain of the amplifier circuit over a range of input levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.