High speed DFEs with direct feedback
US10097383B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2017 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | Aug 2, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03668
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and system of equalizing in a decision feedback equalizer is provided. A plurality of adder circuits receives a digital code representing a previously decided symbol from an output of a prior path of a plurality of paths. A decision-making slicer circuit receives an input voltage and a first clock signal. The plurality of adder circuits receives a second clock signal and injects an offset current proportional to the digital code representing the previously decided symbol into a current injection input of the decision-making slicer circuit, at a first edge of the second clock signal. There is a predetermined skew between the first clock and the second clock to control a timing between the injection of the offset current of the plurality of adder circuits and the initiation of a decision-making phase of the decision-making slicer circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.