Data processor
US10098146B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2016 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | Feb 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/123
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A processor is disclosed. The processor includes a first-receiver-node for receiving a first-receiver-signal, a second-receiver-node for receiving a second-receiver-signal, a first-output-node for coupling to a digital-baseband-processor, a second-output-node for coupling to the digital-baseband-processor and a first-active-data-pipe extending between the first-receiver-node and the first-output-node. The first-active-data-pipe includes a first-analog-to-digital-converter comprising a first-ADC-input coupled to the first-receiver-node and a first-ADC-output coupled to the first-output-node. The first-analog-to-digital-converter is configured to provide a first-digital-signal to the first-output-node. The processor comprises a first-reference-node and a configurable-data-pipe extending between the second-receiver-node and the second-output-node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.