Wafer-to-wafer alignment method

US10100858B2 · kind B2 · utility

Assignee

• CALIFORNIA INSTITUTE OF TECHNOLOGY · US

Inventors

• Cecile D. Jung-Kubiak · Pasadena, US
• Theodore Reck · Oak Ridge, US
• Bertrand Thomas · Bonn, DE
• Robert H. Lin · Chino, US
• Alejandro Peralta · Tecate Mission Road, US
• John J. Gill · La Cañada Flintridge, US
• Choonsup Lee · La Palma, US
• Jose V. Siles · Pasadena, US
• Risaku Toda · Glendale, US
• Goutam Chattopadhyay · Pasadena, US
• Ken B. Cooper · Orange, US
• Imran Mehdi · South Pasadena, US

Key dates

• Filing date: Oct 28, 2016
• Grant date: Oct 16, 2018
• Expiry date: Jul 7, 2037

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10T403/20
• WIPO field: Mechanical elements
• WIPO sector: Mechanical engineering

Abstract

A silicon alignment pin is used to align successive layer of component made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.