Efficient power management of UART interface
US10101797B2 · kind B2 · utility
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12References
25Claims
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Key dates
| Filing date | Sep 27, 2014 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Jul 15, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus relating to efficient and/or robust link power management of a UART (Universal Asynchronous Receiver/Transmitter) interface are described. In an embodiment, logic causes a link to enter into a low power consumption state in response to a message exchange over data lines of a UART (Universal Asynchronous Receiver/Transmitter) interface. The message exchange over the data lines of the UART interface is followed by a modification to one or more flow control signals coupled to the UART interface. Other embodiments are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.