Timer access from user mode through a shared memory page
US10102017B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2013 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Nov 19, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/45583
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system in which a software component executing on a platform can reliably and efficiently obtain state information about a component supported by the platform through the use of a shared memory page. State information may be supplied by the platform, but any state translation information needed to map the state information as supplied to a format as used may be provided through the shared page. In a virtualized environment, the state translation information can be used to map the value of a virtual timer counter or other component from a value provided by a virtual processor to a normalized reference time that will yield the same result, regardless of whether the software component is migrated to or from another virtual processor. Use of a shared page avoids the inefficiency of an intercept into a virtualized environment or a system calls in native mode operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.