Multiple core computer processor with globally-accessible local memories
US10102179B2 · kind B2 · utility
1Cited by
7References
20Claims
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Key dates
| Filing date | Aug 22, 2016 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Aug 22, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.