Shift register, gate driving circuit, array substrate
US10102806B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Jan 5, 2017 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Jan 5, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/061
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A shift register, comprising: a buffer discharging device which controls whether to transfer a signal of a fixed voltage terminal to an output terminal and whether to transfer the signal of the fixed voltage terminal and a signal of a second clock signal terminal to a pull-up node in accordance with a signal of an input terminal, a signal of a reset terminal and a level of a pull-down node; a holding device which controls the level of the pull-down node in accordance with the signal of the second clock signal terminal and a level of the pull-up node; an output device which controls whether to transfer a signal of a first clock signal terminal to the output terminal; a pull-down device which controls whether to transfer the signal of the fixed voltage terminal to the output terminal; a charging device which retains a level of the output terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.