Semiconductor memory device
US10103163B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2016 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Oct 3, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/118
Abstract
A semiconductor memory device is disclosed. The device may include a stack including gate electrodes stacked on a substrate in a vertical direction and insulating patterns interposed between the gate electrodes, vertical channels passing through the stack and connected to the substrate, a tunnel insulating layer enclosing each of the vertical channels, charge storing patterns provided between the tunnel insulating layer and the gate electrodes and spaced apart from each other in the vertical direction, blocking insulating patterns provided between the charge storing patterns and the gate electrodes and spaced apart from each other in the vertical direction, and a bit line crossing the stack and connected to the vertical channels. The blocking insulating patterns may have a vertical thickness that is greater than that of the gate electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.