Manufacture method of array substrate and array substrate manufactured by the method
US10103173B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2016 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Oct 8, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/13625
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present invention provides a manufacture method of an array substrate and an array substrate manufactured by the method. By employing one mask to achieve the via opening process to the flat layer and the first passivation layer, one mask can be saved to decrease the production cost and to reduce the process time; the conductive connection layer covering the first via on the flat layer and the second via on the first passivation layer are formed at the same time while forming the common electrode, and thus to prevent that the source/the drain and the flat layer to be exposed in the environment for eliminating the possibility that the two generate the reaction, which is beneficial for raising the electrical property of the array substrate and realizing the signal conduction. In the array substrate, the signal transmission is smooth, and the substrate possesses the great electrical property.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.