Method of fabricating tunnel transistors with abrupt junctions
US10103226B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2012 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Apr 30, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28194
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a tunnel field effect transistor (TFET) includes forming on a substrate covered by an epitaxially grown source material a dummy gate stack surrounded by sidewall spacers; forming doped source and drain regions followed by forming an inter-layer dielectric surrounding the sidewall spacers; removing the dummy gate stack, etching a self-aligned cavity; epitaxially growing a thin channel region within the self-aligned etch cavity; conformally depositing gate dielectric and metal gate materials within the self-aligned etch cavity; and planarizing the top surface of the replacement metal gate stack to remove the residues of the gate dielectric and metal gate materials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.