Digital power multiplexor
US10103626B1 · kind B1 · utility
6Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2017 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Jul 12, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power multiplexor includes: a first branch including a first transistor coupled in series with a second transistor between a first power supply and a power output; a second branch including a third transistor coupled in series with a fourth transistor between a second power supply and the power output; a controller configured to selectively assert and de-assert a control signal to the first branch and the second branch; a first voltage level shifter coupled between the second transistor and the controller; and a second voltage level shifter coupled between the third transistor and the controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.