Single-stage power converter with power factor correction
US10103636B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 21, 2017 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Sep 21, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P80/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatus for a circuit with power factor correction (PFC) are disclosed. In one or more embodiments, the disclosed method comprises providing, by a single-stage power converter, a delay in phase between a peak current command and a rectified input voltage such that a phase of a transformer current intentionally lags behind a phase of the rectified input voltage to maintain a power factor (PF) level and a total harmonic distortion (THD) level for the single-stage power converter. In one or more analog embodiments, a resistor and a capacitor are implemented into a conventional single-stage power converter to provide the delay in phase between the peak current command and the rectified input voltage. In one or more digital embodiments, a controller within a conventional single-stage power converter exclusively provides the delay in phase between the peak current command and the rectified input voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.