Multiplexer structure
US10103721B2 · kind B2 · utility
0Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2016 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Dec 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1737
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.