Managing integrity of framed payloads using redundant signals
US10103842B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2017 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Jun 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frame error correction circuit may identify and correct errors in data frames provided to a receiver as part of a diversity communications scheme. The frame error correction circuit may further align the data frames so that the data frames can be compared. The frame error correction circuit may perform a bit-wise comparison of the data frames and identify inconsistent bit positions where bits in the data frames differ from one another. Once inconsistent bit positions have been identified, the frame error correction circuit may access a permutation table of permutations of bits at the inconsistent bit positions. In some implementations, the frame error correction circuit uses the permutation table to reassemble permutations of the data frames. In various implementations, the frame error correction circuit performs a CRC of each permutation of the data frames, and provides a valid permutation to a network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.