Electrically testable microwave integrated circuit packaging
US10109537B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2017 |
| Grant date | Oct 23, 2018 |
| Priority date | — |
| Expiry date | Oct 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16251
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped, and singulated. The singulated dies are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Once test probing is complete, the dies and tile are singulated into die/tile assemblies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.