Electronic device package and fabrication method thereof
US10109559B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2014 |
| Grant date | Oct 23, 2018 |
| Priority date | — |
| Expiry date | Aug 27, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic device package and fabrication method thereof is provided. First, a semiconductor substrate is provided and the upper surface of it is etched to from recesses. A first isolation layer is formed on the upper surface and the sidewalls of the recesses. A conductive part is formed to fulfill the recesses and a conductive pad is formed on the first isolation layer to connect the conductive part. An electronic device is combined with the semiconductor substrate on the supper surface, wherein the electronic device has a connecting pad electrically connected to the conductive pad. The semiconductor substrate is thinned form its lower surface to expose the conductive part. A second isolation layer is formed below the lower surface and has an opening to expose the conductive part. A redistribution metal line is formed below the second isolation layer and in the opening to electrically connect to the conductive part.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.