Methods and apparatus for using split N-well cells in a merged N-well block
US10109619B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2016 |
| Grant date | Oct 23, 2018 |
| Priority date | — |
| Expiry date | Jan 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an aspect of the disclosure, a MOS device for reducing routing congestion caused by using split n-well cells in a merged n-well circuit block is provided. The MOS device may include a first set of cells adjacent to each other in a first direction. The MOS device may include a second set of cells adjacent to each other in the first direction and adjacent to the first set of cells in a second direction. The second set of cells each may include a first n-well, a second n-well, and a third n-well separated from each other. The MOS device may include an interconnect extending in the first direction in the second set of cells. The interconnect may provide a voltage source to the first n-well of each of the second set of cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.