Architecture, system, method, and computer-accessible medium for expedited-compaction for scan power reduction
US10110226B2 · kind B2 · utility
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42Claims
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Key dates
| Filing date | Feb 8, 2012 |
| Grant date | Oct 23, 2018 |
| Priority date | — |
| Expiry date | Dec 3, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0008
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Exemplary method, computer-accessible medium, and test configuration can be provided for testing at least one flip-flop. For example, the exemplary test configuration can include at least one scan-out channel having a plurality of regions and a plurality of compactors associated with the plurality of regions. Further, exemplary method, computer-accessible medium, and test configuration can be provided for testing at least on flip-flop that in which at least one scan-out channel having a plurality of regions, a plurality of compactors, and associating the plurality of compactors with the plurality of regions can be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.