Circuits and methods for biasing switch body
US10110271B2 · kind B2 · utility
1Cited by
1References
20Claims
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Key dates
| Filing date | Oct 24, 2017 |
| Grant date | Oct 23, 2018 |
| Priority date | — |
| Expiry date | Oct 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0054
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Described herein are circuits and methods for improving switch performance when overdriving the gate by adding a delay on a PMOS gate voltage such that it can turn on the PMOS during switch state transition to allow charge/discharge of the switch body voltage faster and it can turn off once the process is complete. For example, back-to-back diodes can be used to separate the PMOS gate and drain. This can reduce leakage current and can reduce or eliminate the potential for breakdown of the switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.