Clock synchronization
US10110368B2 · kind B2 · utility
0Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2015 |
| Grant date | Oct 23, 2018 |
| Priority date | — |
| Expiry date | Dec 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L63/083
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In an example embodiment disclosed herein, a first clock is allowed to synchronize with a second clock as long as the time difference between the first and second clocks is less than a predefined limit. If the time difference between the clocks is not less than the predefined limit, the first clock does not synchronize with the second clock until a predefined activity has occurred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.