Methods and apparatus for monitoring aging effects on an integrated circuit
US10114068B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2013 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | May 6, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2879
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit capable of monitoring aging effects on an integrated circuit device is disclosed. The integrated circuit includes a control circuit that obtains a clock signal at different frequencies. A sense circuit may receive the clock signal. First and second control signals may be asserted on the integrated circuit with the control circuit. The first control signal may activate a stress mode, and the second control signal may activate a measurement mode. During stress mode, the sense circuit may receive the clock signal. Any changes in predetermined electrical parameters of one or more transistors in the sense circuit may be monitored and measured during the measurement mode. Aging compensation may be performed when aging effect is detected on the sense circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.