Semiconductor device having register sets and data processing device including the same
US10114555B2 · kind B2 · utility
3Cited by
11References
20Claims
0Family size
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Key dates
| Filing date | Sep 13, 2016 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | Sep 13, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a memory cell array including a first memory region and a second memory region; a plurality of register sets for storing a plurality of parameter sets; and a control logic circuit configured to, activate a first register set among the plurality of register sets in response to a selection signal, and perform an access operation on the first memory region using a parameter set stored in an activated register set from among the plurality of register sets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.