Cache memory system and method for accessing cache line
US10114749B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2017 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | Jun 10, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/314
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory system is provided. The cache memory system includes multiple upper level caches and a current level cache. Each upper level cache includes multiple cache lines. The current level cache includes an exclusive tag random access memory (Exclusive Tag RAM) and an inclusive tag random access memory (Inclusive Tag RAM). The Exclusive Tag RAM is configured to preferentially store an index address of a cache line that is in each upper level cache and whose status is unique dirty (UD). The Inclusive Tag RAM is configured to store an index address of a cache line that is in each upper level cache and whose status is unique clean (UC), shared clean (SC), or shared dirty (SD).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.