Method and system for implementing multi-stage translation of virtual addresses
US10114760B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2014 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | Dec 12, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/682
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method are provided for implementing multi-stage translation of virtual addresses. The method includes the steps of receiving, at a first memory management unit, a memory request including a virtual address in a first address space, translating the virtual address to generate a second virtual address in a second address space, and transmitting a modified memory request including the second virtual address to a second memory management unit. The second memory management unit is configured to translate the second virtual address to generate a physical address in a third address space. The physical address is associated with a location in a memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.