System arbiter with programmable priority levels
US10114776B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2017 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | Apr 27, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable system arbiter for granting access to a system bus among a plurality of arbiter clients and a central processing unit is disclosed. The programmable system arbiter may include one or more interrupt priority registers, each of the one or more interrupt priority registers associated with an interrupt type; and system arbitration logic operable to arbitrate access to the system bus among the plurality of arbiter clients and the CPU based at least on an analysis of a programmed priority order, the programmed priority order comprising a priority order for each of the plurality of arbiter clients, each of a plurality of operating modes of the central processing unit, and each of the one or more interrupt types.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.