Memory-constrained aggregation using intra-operator pipelining
US10114866B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2016 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | Nov 23, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/604
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are system, method, and computer program product embodiments for constraining the amount of memory used during data aggregation. An embodiment operates by separating input data into a plurality of partitions. The embodiment then inserts portions of the input data into blocks from a free list at a given level of a pipeline. The embodiment then inserts the blocks into buffers for processing at a subsequent level of the pipeline. The embodiment processes the inserted blocks at the subsequent level of the pipeline and concatenates the intermediate results into a final aggregate result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.