System and method for monitoring address traffic in an electronic design
US10114912B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 26, 2014 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | Jun 13, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a computer-implemented method for electronic design simulation is provided. Embodiments may include providing, using one or more processors, an electronic design configured to generate one or more address sequences. Embodiments may also include applying an address noise monitor to the electronic design, wherein the address noise monitor is configured to determine address noise data, wherein the address noise data includes a measure of one or more discontinuities in the one or more address sequences. Embodiments may further include simulating the electronic design to generate one or more performance results, the one or more performance results including address noise data. Embodiments may also include generating an address noise profile, based upon, at least in part, the one or more performance results including address noise data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.