Physical placement control for an integrated circuit based on state bounds file
US10114918B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 27, 2016 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | Jul 14, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein are directed to systems and methods for controlling physical placement of a circuit design. The systems and methods may extract state groups of the circuit design by deriving state groups from each logical hierarchy of the circuit design. At each level, available state points may be grouped by similarity and stored in a state groups collection alongside grouping terms. The systems and methods may generate a state bounds file that bounds locations of the state points in the circuit design. The state bounds file may be based on the extracted state groups and the grouping terms stored in the state groups collection. The systems and methods may control physical placement of the circuit design using the state bounds file.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.