Integrated circuits with SRAM devices having read assist circuits and methods for operating such circuits
US10115453B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2016 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | Jan 25, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Integrated circuits including semiconductor memory devices, read assist circuits for semiconductor memory devices, and methods for operating such circuits are provided. In an embodiment, a read assist circuit for use in a semiconductor memory device is provided. The read assist circuit includes a first drive device for driving a wordline of the semiconductor memory device to a wordline driving voltage. The first drive device operates at a first current. The read assist circuit also includes a second drive device for maintaining the wordline of the semiconductor memory device at the wordline driving voltage. The second drive device operates at a second current lower than the first current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.