External connection mechanism, semiconductor device, and stacked package
US10115649B1 · kind B1 · utility
3Cited by
1References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 21, 2017 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | Dec 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/81444
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device encompasses a connecting base including a semiconductor substrate and a surface insulating-film on the semiconductor substrate, a passivation film covering the surface insulating-film and surface electrode on the surface insulating-film, establishing a groove that exposes a central part of the surface electrode, a barrier-metal film spanning from the bottom of the groove to an upper face of the passivation film, and micro-bumps arranged on the barrier-metal film located on the passivation film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.