Solder layer of a semiconductor chip arranged within recesses
US10115693B2 · kind B2 · utility
2Cited by
1References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 12, 2014 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | Mar 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One semiconductor chip includes a substrate having insulation properties, a plurality of bump electrodes provided on one surface of the substrate, a plurality of recesses provided in the other surface of the substrate, and a solder layer disposed within the recesses. The recesses are formed such that the area of the opening decreases from the other surface side toward the one surface side of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.