Bitline boost for fast settling with current source of adjustable bias
US10116892B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2017 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | Dec 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/18
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A photodiode is adapted to accumulate image charges in response to incident light. The accumulate image charges are transferred to a floating diffusion, amplified, row selected and the amplified row selected signal is output to a bitline. A bitline enable transistor is coupled to link between the bitline and a bitline source node. A current source is coupled to connect between the bitline source node and a ground. The current source generator sinks adjustable current from the bitline source node to the ground through a cascode transistor and a bias transistor. A cascode hold capacitor is coupled between the cascode control voltage and the ground. A bias hold capacitor is coupled between the bias control voltage and the ground. A bias boost driver is coupled to control the cascode control voltage and the bias control voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.