Multi-chip reference counting power management
US10120427B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2016 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | Nov 12, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A payment reader includes a power management system to control the power mode of the payment reader. The power management system can transition the payment reader between a sleep mode, a low power mode and a full power mode. The power management system can use a low power mode reference counter to determine when to transition from the full power mode to the low power mode and a sleep mode reference counter to determine when to transition from the low power mode to the sleep mode. When the low power mode reference counter reaches zero, the power management system deactivates a payment processing subsystem to transition to the low power mode. Similarly, when the sleep mode reference counter reaches zero, the power management system deactivates a payment reader system to transition to the sleep mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.