Compare and delay instructions
US10120681B2 · kind B2 · utility
4Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2014 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | Nov 11, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/455
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A delay facility is provided in which program execution may be delayed until a predefined event occurs, such as a comparison of memory locations results in a true condition, a timeout is reached, an interruption is made pending or another condition exists. The delay facility includes one or more compare and delay machine instructions used to delay execution. The one or more compare and delay instructions may include a 32-bit compare and delay (CAD) instruction and a 64-bit compare and delay (CADG) instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.