Patent · US Active

Hardware controlled instruction pre-fetching

US10120713B2 · kind B2 · utility

4Cited by

2References

19Claims

0Family size

Assignee

NXP USA, Inc. · US

Inventors

Michael Rohleder · Unterschleißheim, DE
Stefan Singer · Vaterstetten, DE
Jochen Gerster · Stuttgart, DE

Key dates

Filing date	Jul 5, 2016
Grant date	Nov 6, 2018
Priority date	—
Expiry date	Mar 10, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/461
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A task control circuit maintains, in response to task event information, a task information queue that includes task information for a plurality of tasks. Based upon the task information in the task information queue, a future task switch condition is identified as corresponding to a task switch time for a particular task of the plurality of tasks. A load start time is determined for a set of instructions for the particular task. A pre-fetch request is generated to load the set of instructions for the particular task into the memory circuit. The pre-fetch request is forwarded to a hardware loader circuit. In response to the task switch time, a task event trigger is generated for the particular task. The hardware loader circuit is used to load, in response to the pre-fetch request, the set of instructions from a non-volatile memory into the memory circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.