Patent · US Active

System and method for cache memory line fill using interrupt indication

US10120819B2 · kind B2 · utility

1Cited by

4References

20Claims

0Family size

Assignee

NXP USA, Inc. · US

Inventors

Michael Rohleder · Unterschleißheim, DE
Stefan Singer · Vaterstetten, DE
Josef Fuchs · Appenzell, CH

Key dates

Filing date	Mar 20, 2017
Grant date	Nov 6, 2018
Priority date	—
Expiry date	Aug 3, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/60
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An embedded computer system includes a processor, an interrupt source, an interrupt controller and a cache memory subsystem. In response to a request from the processor to read a data element, the cache memory subsystem fills cache lines in a cache memory with data elements read from an upper-level memory. While filling a cache line the cache memory subsystem is unable to respond to a second request from the processor which also requires a cache line fill. In response to receiving an indication from an interrupt source, the interrupt controller provides an indication substantially simultaneously to the processor and to the cache memory subsystem. In response to receiving the indication from the interrupt controller, the cache memory subsystem terminates a cache line fill and prepares to receive another request from the processor.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.